Publications: List of my publications

 

Recent Publications:

 

In 2011

 

1.    Pramod Subramanyan, Virendra Singh, Kewal Saluja, and Erik Larsson, `Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors`, 29th IEEE International Conference on Computer Design (ICCD) 2011, Amherst, MA, USA, October 2011

2.    Mohammed Abdul Razzaq, Virendra Singh, and Adit Singh, `SSTKR: Secure and testable scan design through test key randomization`, 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov. 2011

3.    Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Test and diagnosis of analog circuits using moment generating functions`, 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov. 2011

4.    Manas Puthal, Virendra Singh, MS Gaur and Vijay Laxmi, `C-Routing: An adaptive hierarchical NoC routing methodology`, 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2011, Hongkong, China, October 2011

5.    Anzhela Matrosova, Virendra Singh, Alexey Melnikov, and Ruslan Mukhamedov, `Selection of state variables for partially enhanced scan`, 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011

6.    Mohammad Abdul Razzaq, Alok Baluni, Ram Rakesh Jangir, Virendra Singh, and Masahiro Fujita, `On synthesis of degradation aware circuits at higher level of abstraction`, 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011.

7.    Pawan Kumar and Virendra Singh, Efficient regular expression pattern matching using cascaded automata architecture for network intrusion detection system`, 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011.

8.    V. Prasanth, Virendra Singh, and Rubin Parekhji, `Reduced overhead soft error mitigation methodology using error control coding technique`, 17th IEEE International On-Line Test Symposium (IOLTS) 2011, Athens, Greece, July 2011.

9.    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Level of confidence evaluation and its usage for roll-back recovery and checkpoint optimization`, Workshop on Dependable and Secure Nanocomputing (WDSN) 2011, Hongkong, China, May 2011

10.  Vinutha Konandur, Virendra Singh, MS Gaur, and Anzhela Matrosova, `Fault Grading at Higher Level of Abstraction`, IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May 2011

11.  A. Matrosova, S. Ostanin, A. Milnikov, and Virendra Singh, `Using AND-OR tree for path delay faults`,  IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May 2011

12.  Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Study on level of confidence for rollback recovery with check-pointing`,  Workshop on Dependability Issues in Deep-submicron Technologies (DDT) 2011, Trondheim, Norway, May 2011

13.  Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Nonlinear analog circuit test and diagnosisunder process variation using V-transform coefficients`, 29th IEEE VLSI Test Symposium (VTS), 2011, California, USA, May 2011

14.  Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Testing linear and non-linear analog circuits using moment generation functions`, 12th IEEE Latin American Test Workshop (LATW) 2011, Porto de Galinhas, Brazil, March 2011

15.  Chao Han, Adit Singh, and Virendra Singh, `Efficient partial enhanced Scan for high coverage delay testing`, 2011 Joint IEEE International Conference on Industrial Technology and 43rd Southeastern Symposium on System Theory (ICIT-SSST) 2011, Auburn, USA, March 2011

16.  Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Distinguishing process variation induced faults from manufacturing defects in analog circuits using V-transform coefficients`,  2011 Joint IEEE International Conference on Industrial Technology and 43rd Southeastern Symposium on System Theory (ICIT-SSST) 2011, Auburn, USA, March 2011

17.  Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, `SEU tolerant SRAM cell`, International Symposium on Quality Electronic Design (ISQED) 2011, Santa Clara, CA, USA, March 2011

18.  Naveen Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `Traffic aware topology generation methodology for application specific NoC`, IEEE International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan 2011

19.  Navaneeth Rameshan, Mark Zwolinski, Vijay Laxmi, M.S. Gaur, Virendra Singh, and Lalith P., `Acceleration of functional validation using GPGPU`, IEEE International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan 2011

In 2010

20.  [Book Chapter] Dimitar Nikolov, Mikael Vayrynen, Urban Ingelson, Virendra Singh, and Erik Larsson, `Optimizing Fault Tolerance for Multi-Processor System-on-Chip`, Design and Test Technology for Dependable Systems-on-Chip, Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, 2010, Hardcover, ISBN:978-1-6096-0212-3.

21.  Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, `SEU tolerant SRAM for FPGA application`, International Conference on Field Programmable Technology (FPT) 2010, Beijing, Dec 2010

22.  Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, and Adit Singh, `A modified scan flip-flop for test power reduction`, 19th IEEE Asian Test Symposium (ATS) 2010, Shanghai, China, Dec 2010

23.  Jaynarayan Tudu, Erik Larsson, and Virendra Singh, `Test Scheduling of modular system-on-chip under capture power constraints`, 11th IEEE Workshop on RTL and High Level Test (WRTLT) 2010, Shanghai, China, Dec 2010

24.  Naveen Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `Energy Aware Design Methodologies for Application Specific NoC`, 28th Norchip Conference (NORCHIP), 2010, Tampere, Finland, Nov 2010

25.  Anzhela Matrosova, Valeriy Lipsky, Aleksey Melnikov, and Virendra Singh, `Path delay faults and ENF`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010

26.  Vinay N.S, Indira Rawat, Erik Larsson, M.S. Gaur, and Virendra Singh, `Thermal aware test scheduling for stacked multi-chip modules`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010.

27.  K.R. Vinutha, Virendra Singh, Anzhela Matrosova, and M.S. Gaur, `Fault grading using instruction-execution graph`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010.

28.  Adit Kajala, Gayaprasad Sinsinwar, Rahul Choudhary, Jaynarayan Tudu, and Virendra Singh, `On selection of state variables for delay test of identical functional units`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010

29.  Gayaprasad Sinsinwar, Rahul Choudhary, Aditi kajala, and Virendra Singh, `Test program generation for simultaneous testing of multiple identical functional units`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersberg, Russia, Sep 2010

30.  Prasanth V., Virendra Singh, and Rubin Parekhji, `Robust detection of soft errors using delayed capture methodology`, IEEE International Online Testing Symposium (IOLTS) 2010, Corfu, Greece, July 2010

 

31.  Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Energy ffficient fault tolerance in chip multiprocessors using critical value forwarding`, 40th IEEE International Conference on Dependable Systems and Networks (DSN), Chicago, IL, USA, June 2010.

 

32.  Abhishek A., Amanulla Khan, Virendra Singh, Kewal Saluja, and Adit Singh, `Test application time minimization for RAS using basis optimization of column decoder`, IEEE International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France, May 2010.

 

33.  Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Genetic algorithm based topology generation for application specific network-on-chip`, IEEE International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France, May 2010.

 

34.  Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, and Adit Singh, `Modified T-FF bases scan cell for RAS`, 15th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May 2010.

 

35.  Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach`, 15th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May 2010.

 

36.  Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Power efficient redundant execution for chip multiprocessors`, Great Lake Symposium on VLSI (GLSVLSI) 2010, Providence, Rhode Island, USA May 2010.

 

37.  Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Graph theoretic approach for scan cell reordering to minimize peak shift power`, 20th ACM Great Lake Symposium on VLSI (GLSVLSI) 2010, Providence, Rhode Island, USA May 2010

 

38.               Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Mapping and scheduling of jobs in homogeneous NoC-based MPSoC`, 10th Swedish System-on-Chip Conference, Kolmarden, Sweden, May 2010

 

39.  Pramod Subramanyam, Virendra Singh, Kewal Saluja, and Erik Larsson, `A low cost redundant execution architectures for Chip multiprocessors`, Design Automation and Test in Europe (DATE) 2010, Dresden, Germany, March 2010.

 

40.  L. Suresh, N. Rameshan, A. Narayan, M. Zwolinski, M.S. Gaur, V. Laxmi, and V. Singh, `EDA design flow acceleration by GP-GPU`, 2nd Workshop on Designing for embedded parallel computing plateform: Architectures, design tools, and applications (in conjunction with DATE 2010) 2010, Dresden, Germany, March 2010.

 

41.  Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Fast energy aware application specific network-on-chip topology generator`, IEEE International Advanced Computing Conference 2010, Patiala, India, Feb 2010.

 

42.  Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Estimating error probability and its application for optimizing roll-back recovery with checkpointing`, IEEE Symposium on Electronic Design, Test & Applications (DELTA) 2010, Ho Chi Minh , Vietnam, Jan 2010

 

43.  Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `On-line techniques to adjust and optimize checkpointing frequency`, IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2010, Bangalore, India, Jan 2010

 

44.  Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, Hideo Fujiwara, and Adit Singh, `On Minimization of Test Application Time for RAS`, 23rd International Conference on VLSI Design (ICVD) 2010, Bangalore, Jan 2010.

 

45.  Suraj Sindia, Virendra Singh, and Vishwani D. Agrawal, `Parametric Fault Diagnosis of Nonlinear Analog Circuits using Polynomial Coefficients`, 23rd International Conference on VLSI Design (ICVD) 2010, Bangalore, Jan 2010.

 

In 2009

 

46.  Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip`, IEEE INDICON 2009, Gandhi Nagar, India, Dec 2009.

 

47.  Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Designing Application Specific Irregular Topology for Network-on-Chip`, 17th International Conference on Advanced Computing and Communications (ADCOM) 2009, Bangalore, Dec 2009.

 

48.  Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Scan Cells Reordering to Minimize Peak Power during Scan Testing of SoC`, IEEE WRTLT 09, Hong Kong, Nov. 2009.

 

49.  Venkat Rajesh, Erik Larsson, MS Gaur, and Virendra Singh, `An Even Odd DFD Technique for Scan Chain Diagnosis`, IEEE WRTLT 09, Hong Kong, Nov. 2009.

 

50.  Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `Multi-tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients`, IEEE Asian Test Symposium (ATS) 2009, Taichung, Taiwan, Nov 2009.

 

51.  Deepak K.G., Robinson Reyna, Virendra Singh, and Adit Singh, `Leveraging Partial Enhanced Scan for Improved Observabilty in Delay Fault Testing`, IEEE Asian Test Symposium (ATS) 2009, Taichung, Taiwan, Nov 2009.

 

52.  Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `V-Transform: An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits`, IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia, Sep 2009.

 

53.  Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, and Virendra Singh, `Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation`, IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia, Sep 2009.

 

54.  Viney Kumar, Rahul Raj, and Virendra Singh, `FREP: A Soft-Error Resilient Pipelined RISC Architecture`, IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia, Sep 2009.

 

55.  Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Adit Singh, `Capture Power Reduction for Modular System-on-Chip Test`, IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 2009.

 

56.  Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing`, IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 2009.

 

57.  Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Power Efficient Redundant Execution for Chip Multiprocessor`, Workshop on Dependable and Secure Nanocomputing (WDSN) 2009, Lisbon, Portugal, June 2009.

 

58.  Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Vishwani D. Agrawal, `On Minimization of Peak Power during SoC Test`, IEEE European Test Symposium (ETS) 2009, Seville, Spain, May 2009.

 

59.  Suraj Sindia, Virendra Singh, and Vishwani D. Agrawal, `Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits`, 18th IEEE North Atlantic Test Workshop (NATW) 2009, New York, USA, May 2009.

 

60.  Reshma Jumani, Niraj Jain, Virendra Singh, and Kewal K. Saluja, `DX-Compactor: Distributed X-Compaction for SoC Test`, ACM Annual Great Lake Symposium on VLSI (GLSVLSI) 2009, Boston, USA, May 2009.

 

 

61.  Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `Coefficient-Based Parametric Testing of Non-Linear Analog Circuits`, ACM Annual Great Lake Symposium on VLSI (GLSVLSI) 2009, Boston, USA, May 2009.

 

62.  Mikael Vayrynen, Virendra Singh, and Erik Larsson, `Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on-Chips`, Intl. Conference on Design Automation and Test in Europe (DATE) 2009, Nice, France, Apr 2009.

 

63.  Vinay NS, Erik Larsson, and Virendra Singh, `Thermal Aware Test Scheduling of Stacked Multi-Chip Modules`, Workshop on 3D Integration (In conjunction with DATE 2009), Nice, France, Apr 2009.

 

 

Selected Publications (before 2008):

 

  • Virendra Singh and Erik Larsson, `On Reduction of Capture Power for Modular System-on-Chip Test`, 9th IEEE WRTLT 2008, pp. 35-40, Sapporo, Japan, Nov 2008.

 

  • Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Instruction-Based Self-Testing of Delay Faults in Pipelined Processors`, IEEE Trans. on VLSI Systems, Vol. 14, No. 11, Nov. 2006, pp. 1203-1215.

 

  • Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Program-Based Testing of Superscalar Microprocessor`, Proceedings of the IEEE 14th North Atlantic Test Workshop, May 2005, pp. 79-86, Berlington, VT, USA, May 2005.

 

  • Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Delay Fault Testing of Processor Cores in Functional Mode`, IEICE Trans. on Information & Systems, Vol. E-88D, No. 3, March 2005, pp. 610-618.

 

 

Full List of my publications