Design and Test have always led an uneasy co-existence. Designers have viewed Test as encroaching on their performance and area goals, and placing unnecessary bounds on their creativity. However, rising cost of Test and increasing limitations of available tester platforms continue to place additional requirements on design. Traditional testing methods utilizing stuck-at and transition fault models are no longer adequate to achieve target quality in many designs.

Today, Testing needs to address defects and failure modes due to process, thermal and voltage variations. Complexity of test pattern development against physical fault models that account for parametric variations appear insurmountable. Reduced manufacturing tolerance due to sub-wavelength lithography, time dependent device degradation along with interplay with ambient factors such as temperature and voltage necessitates new methods merged with fault tolerant designs while continue to address the test problem.

Prof. Hideo Fujiwara over the course of his illustrious career has devoted his energies to solving problems similar to and beyond those mentioned above. His research in VLSI Testing runs the gamut from ATPG, complexity theory, and Design for Test. This workshop seeks to celebrate Prof. Fujiwara`s contribution to the field of VLSI Testing, and his efforts in fostering original thinking as a dedicated educator and mentor.

The major goals of the workshop are:

- to highlight Prof. Fujiwara`s significant contributions

- to bring together Prof. Fujiwara`s students, associates, friends, and fans for a memorable reunion

The symposium will feature three types of presentations:

- Invited talks from well known people in academia/industry

- Research summaries by various students and associates

- Informal talks during dinner time bringing back memories

Websites:

o Workshop: http://www.serc.iisc.ernet.in/~viren/WHF/

o ATS: www.ecs.umass.edu/ece/ats11/

o WRTLT: www.ieee-wrtlt.org

For general information, please contact:

Virendra Singh

Indian Institute of Science, Bangalore, India

E-mail: viren@serc.iisc.ernet.in, virendra@computer.org

Tel: +91-80-2293-3421

Mob: +91-95535-22109