SE-273 (3:1): Processor Design

Semester: Jan-Apr 2008

Instructor: Virendra Singh

Class Hours: 8:15 - 9:45 AM (MWF) @202, SERC

Syllabus:

Introduction to Verilog HDL and logic synthesis. VLSI implementation of various architectures.

CISC Processor Design: Defining microprocessor, hardware flowchart, implementing from flowchart, exception, control store, microcode design

RISC Processor Design: Building datapath and controller, single cycle implementation, multi cycle implementation, pipelined implementation, exception and hazards handling

Superscalar Processors Design: Superscalar organization, superscalar pipeline overview, VLSI implementation of dynamic pipelines, register renaming, reservation station, re-ordering buffers, branch predictor, and dynamic instruction scheduler etc.; simultaneous multi-threading (SMT) design

Impact of physical technology, trends in power consumption, low power techniques, low voltage techniques, clock distribution.

Verification and test issues.

References:

1. Nick Tredennick, Microprocessor Logic Design, Digital Press, 1987
2. DA Patterson and JL Hennessy, Computer Organization and Design, Morgan Kaufman Pub., N. Delhi, 2005
3. JP Shen and MH Lipasti, Modern Processor Design, McGraw Hill, Crowfordsville, 2005
4. Mike Johnson, Superscalar Microprocessor Design, Prentice Hall, Englewood Cliffs, NJ, 1991
5. A. Chandrakasan, WJ Bowhill, and F. Fox, Design of High Performance Microprocessor Circuits, IEEE Press
6. OpenSparc T1 manual, http://www.opensparc.net/
7. Current Literature

Pre-requisite:

Knowledge of Digital System Design and Computer Architecture

Test Schedule:

Test1: Feb 27 (Wed) at 8:15 AM

Test2: Mar 31 (Mon) at 8:15 AM

Test3: Apr 16 (Wed) at 8:15 AM

Assignment 1: Due on Mar 14 (Fri) upto 10:00 am

Assignment 2: Due on May 3 (Sat)

Final Exam: April 21, 2008 (0900 - 1200 hrs) @202, SERC

Lecture Schedule:

Jan 9	Course Introduction
Jan 14	High Level Synthesis - I	High Level Synthesis
Jan 16	Verilog- I (By Prof. Bharadwaj Amrutur)	Verilog
Jan 18	High Level Synthesis - II	Scheduling and Binding
Jan 21	CISC Processor Design - I	CISC Architecture
Jan 23	Verilog - II (By Prof. Bharadwaj)	Verilog
Jan 25	CISC Processor Design - II	Hardware Flowcharts
Jan 28	CISC Processor Design - III	Hardware Flowcharts (Level1)
Jan 30	Verilog - III (By Prof. Bharadwaj)
Feb 1	CISC Processor Design - IV	Hardware Flowcharts (Level2)
Feb 4	CISC Processor Design - V	Implementation from Flowchart
Feb 6	CISC Processor Design - VI	Implementation – Exceptions, Overlap
Feb 8	CISC Processor Design - VII	Performance improvement
Feb 13	RISC Processor Design - I	CISC vs RISC, RISC Instruction Set
Feb 15	RISC Processor Design - II	DLX Instruction set
Feb 18	RISC Processor Desihn - III	DLX - Level 1 HFC
Feb 20	RISC Processor Design - IV	DLX - Level 2 HFC
Feb 22	RISC Processor Design - V	DLX - Implementation from HFC
Feb 25	RISC Processor Design - VI	DLX - Implementation from HFC
Feb 27	Test1
Feb 29	RISC Processor Design - VII	DLX - Exception, Interrupt, and special instruction implementation
Mar 3	RISC Processor Design - VIII	Single cycle implementation - MIPS
Mar 7	RISC Processor Design - IX	Multi-cycle implementation - MIPS
Mar 12	Memory System Design - I (By Prof. Bharadwaj)	Memory Design - Caches
Mar 14	Pipelined Processor Design - I	Pipelined Design - MIPS
Mar 17	Pipelined Processor Design - II	Pipelined Design - MIPS
Mar 19	Memory System Design - II (By Prof. Bharadwaj)	Memory Design - Caches
Mar 24	Pipelined Processor Design - III	Pipelined Design - MIPS
Mar 26	Superscalar Design - I	Superscalar Architecture
Mar 28	Memory System Design (by Prof. Bharadwaj)
Mar 31	Test 2
Apr 02	Superscalar Design - II	Superscalar Design – Instr. Fetch Unit
Apr 04	Superscalar Design - III	Superscalar Design – Execution Unit
Apr 07	Superscalar Design - IV	Superscalar Design – Tomasulo algorithm
Apr 09	Superscalar Design -V	Advanced technques

Selected Readings (Papers):