3rd  IEEE International Workshop on Reliability Aware System Design and Test

(In conjunction with the International Conference on VLSI Design)

HICC, Hyderabad, India   January 7-8, 2012



Organizing Committee

General Co-Chairs

Adit Singh (Auburn U., US)

Virendra Singh (IISc, IN)

General Vice Co-Chairs

Michiko Inoue (NAIST, JP)

Sreejit Chakravarty (LSI, US)

Program Co-Chairs

Erik Larsson (Linkoping U. SE)

Rubin Parekhji (TI, IN)

Program Vice Co-Chairs

Ilia Polian (Passau U., DE)

MS Gaur (MNIT, IN)

Organizing Committee Co-Chairs

Bhargab Bhattacharya (ISI, IN)

V. Kamakoti (IITM, IN)

Publication Chair

Vijay Laxmi (MNIT, IN)

Finance Co-Chair

Pradip Thaker (Beeceem, IN)

S. Ramakrishnan (WT, IN)

Publicity Chair:

Susanta Chakravarty (BESU, IN)

Chia Yee Ooi (TUM, MY)

Local Arrangement chair


Website management chair

Sushil Kabra (BSNL, IN)

Registration Chair

Jaynarayan Tudu (IISc, IN)

Arjun Chiluka (IISc, IN)


Steering Committee:


K.K. Saluja (US)  – Chair

J.A. Abraham (US)

V.D. Agrawal (US)

B. Al-Hashimi (UK)

B. Becker (DE)

A. Chatterjee (US)

H. Fujiwara (JP)

M. Fujita (JP)

E. Larsson (SE)

R. Parekhji (IN)

S.M. Reddy (US)

A.D. Singh (US)

V. Singh (IN)



Program Committee:





Even as advances in CMOS technology come up against physical limits of material properties and lithography, raising many new challenges that must be overcome to ensure IC quality and reliability, there appears to be no obvious alternate technology that can replace End-of-Roadmap CMOS over the next decade. However, many reliability challenges from increasing defect rates, manufacturing variations, soft errors, wearout, etc. will need to be addressed by innovative new design and test methodologies if device scaling is to continue on track as per Moore’s Law to 10nm and beyond. The key objective of this annual workshop, planned to be held in conjunction with the International Conference on VLSI Design, is to provide an informal forum for vigorous creative discussion and debate of this area. The aim is to encourage the presentation and discussion of truly innovative and “out-of-the-box” ideas that may not yet have been fully developed for presentation at reviewed conferences to address these challenges.  Additionally, the workshop invites embedded talks and tutorials on cutting edge topics related to reliability aware design of CMOS and hybrid nanotechnology systems.

Representative topics include, but are not limited to:

- Design for test,

- Built-in self-test

- ATPG and defect oriented test

- Delay test

- Low power test

- Instruction-based self-test

- On-line test methodology

- Reliability of CMOS circuits

- Self checker circuits

- Self diagnosis methods

- Fault tolerant micro-architecture

- Self-healing system design

- Energy and performance aware fault -tolerant micro-architectures

- Device degradation and mitigation

- System validation methodology

- Secure system design

- Design for reliability, dependability, and verifiability


Authors are invited to submit previously unpublished technical proposals. The proposals must be full papers not to exceed 6 pages. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and 6 to 7 keywords.  Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address. Submit a copy of your proposal in PDF either online submission via workshop website http://www.serc.iisc.ernet.in/~viren/RASDAT12/

Submissions are due no later than October 21, 2011. Authors will be notified of the disposition of their presentation by November 15, 2011 Authors of accepted presentations must submit the final paper by December 1, 2011 for inclusion in the Workshop Proceedings, which will be provided to the attendees.

General Information

Adit Singh

Auburn University, Auburn,  USA

E-mail: adsingh@auburn.edu

Tel: +1.334.644.1647

Fax: +1.334.844.1809

Virendra Singh

Indian Institute of Science, Bangalore, India

E-mail: viren@serc.iisc.ernet.in

Tel: +91.80.2293.3421

Fax: +91.80.2360.2648


Program Related  Information

Rubin Parekhji

Texas Instruments, Bangalore, India



Erik Larsson

Linkoping University, Sweden