IEEE International Workshop on Reliability Aware System Design and Test 2012

Advance Program (pdf

)

Day 1 (January 7, 2012 - Saturday)

2:00 pm - 2:15 pm	Inauguration
2:15 pm - 3:00 pm	Keynote Address - I Speaker: Rajesh Gupta, UCSD
3:00 pm - 3:30 pm	Invited Talk - I Speaker:Niklas Hallberg, Swedish Defence Research Agency
3:30 pm - 4:00 pm	COFFEE
4:00 pm - 5:30 pm	Session - I

Day 2 (January 8, 2012 - Sunday)

9:00 am - 9:45 am	Keynote Address - II Speaker: A.N. Chandorkar, IIT Bombay
9:45 am - 10:15 am	Invited Talk - II Speaker: Seiji Kajihara, Kyushu Institute of Technology
10:15 am - 10:30 am	COFFEE
10:30 am - 11:45 am	Session - II
11:45 am - 12:15 pm	Invited Talk - III Speaker: V. Kamakoti, IIT Madras
12:15 pm - 1:30 pm	LUNCH
1:30 pm - 2:00 pm	Invited Talk - IV
2:00 pm - 3:30 pm	Session - III
3:30 pm - 4:00 pm	COFFEE
4:00 pm - 4:30 pm	Invited Talk - V
4:30 pm - 5:30 pm	Panel Discussion
5:30 pm - 5:40 pm	Closing

Session-I: Power Aware Test

S1.1 Test Planning for Core-based 3D Stacked ICs under Power Constraints
S1.2 Low power scan flop design to eliminate output gating performance overhead for Critical paths
S1.3 Modeling and Testing of Multi-cycle Power Droop Faults

Session - II: RELIABILITY - I

S1.1: A Highly Robust And Cost Effective SEU Tolerant Memory Cell
S1.2:Evaluating Impact of Soft-Errors in an Embedded System
S1.3: Improved Error Resilience for Huffman Compression with Hamming Code Based Technique

Session - II: Reliability - II

S3.1 Reliability Evaluation of Redundancy based Fault Tolerant Techniques at Nanoscale

S3.2 Stress Accelerated Electrical Reliability Qualification of Mixed-Signal SoC - Theory, Practice and Challenges of Power Management, Analog Integration

S3.3 Evaluation of Circuit Reliability based on Distribution of Different Signal Input Patterns
S3.4 Sensitivity Analysis of Probability Transfer Matrix on same Functionality Circuit Architectures