RASDAT`10

IEEE International Workshop on Reliability Aware System Design and Test

Even as advances in CMOS technology come up against physical limits of material properties and lithography, raising many new challenges that must be overcome to ensure IC quality and reliability, there appears to be no obvious alternate technology that can replace End-of-Roadmap CMOS over the next decade. However, many reliability challenges from increasing defect rates, manufacturing variations, soft errors, wearout, etc. will need to be addressed by innovative new design and test methodologies if device scaling is to continue on track as per Moore`s Law to 10nm and beyond. The key objective of this annual workshop, started in conjunction with the International Conference on VLSI Design in 2010, is to provide an informal forum for vigorous creative discussion and debate of this area. The aim is to encourage the presentation and discussion of truly innovative and `out-of-the-box` ideas that may not yet have been fully developed for presentation at reviewed conferences to address these challenges. Additionally, the workshop includes embedded talks and tutorials on cutting edge topics related to reliability aware design of CMOS and hybrid nanotechnology systems.

Representative topics include, but are not limited to:

-Design for test,

- Built-in self-test

- ATPG and defect oriented test

- Delay test

- Low power test

- Instruction-based self-test

- On-line test methodology

- Reliability of CMOS circuits

- Self checker circuits

- Self diagnosis methods

- Fault tolerant micro-architecture