SE-273 (3:1): Processor Design

Semester: Jan-Apr 2010

Instructor: Virendra Singh

Class Hours: 9:00 - 10:00 AM (MWF) @202, SERC

Syllabus:

Introduction to Verilog HDL and logic synthesis. VLSI implementation of various architectures.

CISC Processor Design: Defining microprocessor, hardware flowchart, implementing from flowchart, exception, control store, microcode design

RISC Processor Design: Building datapath and controller, single cycle implementation, multi cycle implementation, pipelined implementation, exception and hazards handling

Superscalar Processors Design: Superscalar organization, superscalar pipeline overview, VLSI implementation of dynamic pipelines, register renaming, reservation station, re-ordering buffers, branch predictor, and dynamic instruction scheduler etc.; simultaneous multi-threading (SMT) design

Impact of physical technology, trends in power consumption, low power techniques, low voltage techniques, clock distribution.

Verification and test issues.

References:

1. Nick Tredennick, Microprocessor Logic Design, Digital Press, 1987
2. DA Patterson and JL Hennessy, Computer Organization and Design, Morgan Kaufman Pub., N. Delhi, 2005
3. JP Shen and MH Lipasti, Modern Processor Design, McGraw Hill, Crowfordsville, 2005
4. Mike Johnson, Superscalar Microprocessor Design, Prentice Hall, Englewood Cliffs, NJ, 1991
5. A. Chandrakasan, WJ Bowhill, and F. Fox, Design of High Performance Microprocessor Circuits, IEEE Press
6. OpenSparc T1 manual, http://www.opensparc.net/
7. Current Literature

Pre-requisite:

Knowledge of Digital System Design and Computer Architecture

Test Schedule:

Test1: Feb 19 (Friday) at 9:00 am - Open Book

Test2: Mar 19 (Friday) at 9:00 am - Open Book

Test3: Apr 9 (Friday) at 9:00 am - Open Book

Assignment 1: March 1 (Monday) 5:00 pm

Assignment 2: April 2 (Monday) 5:00 pm

Project: Apr 29 (Thursday) - Midterm (Apr 2)

Final Exam: Apr 22 (Thursday) 9:00 am - 12:00 noon @212, SERC - Open Book

Evaluation: Test - 20%, Assignments - 20%, Project - 20%, Final Exam - 40%

Lecture Schedule:

Jan 6	Course Introduction
Jan 13	Introduction	History of computer design
Jan 15	CISC Processor Design - I	CISC Architecture
Jan 18	CISC Processor Design - II	Hardware Flowcharts
Jan 20	CISC Processor Design - III	Hardware Flow Chart
Jan 22	CISC Processor Design - IV	Implementation from Hardware Flow Chart
Jan 25	CISC Processor Design - V	Implementation from Hardware Flow Chart
Jan 27	CISC Processor Design -VI	Performance Enhancement
Jan 29	RISC Architecture	Introduction to RISC Architecture
Feb 1	RISC - Hardware Flowchart	Datapath organization and hardware flowchart
Feb 3	RISC - Hardware Flowcharts	DLX hardware flowchart
Feb 8	No Class
Feb 10	RISC Implementation	DLX Implementation
Feb 13	RISC Implementation RISC-Single Cycle implementation	Exceptions and Interrupts MIPS Single cycle implementation
Feb 15	RISC-Multicycle implementation	MIPS multi cycle implementation
Feb 17	RISC-Multicycle implementation	MIPS multicycle implementation
Feb 19	TEST-1
Feb 22	Pipelined Processor Design
Feb 24	Pipelined Implementation-MIPS
Feb 26	Beyond Pipelining
Mar 1	Superscalar Architecture
Mar 3	Superscalar Pipelines
Mar 5	Superscalar Architecture
Mar 15	Superscalar Architecture
Mar 17	Memory Architecture By Amrutur Bharadwaj
Mar 19
Mar 22
Mar 24	TEST -2
Mar 26	Superscalar Architecture
Mar 29	Superscalar Architecture
Mar 31	Superscalar Architecture
Apr 2	Superscalar Architecture
Apr 5	Superscalar Architecture
Apr 7	Superscalar Architecture
Apr 9	Superscalar Architecture
Apr 10	Superscalar Case Study - P6 SMT Architecture
Apr 12	SMT Architecture
Apr 14	TEST -3
Apr 16	SMT Architecture and Fault Tolerance
Apr 22	FINAL EXAM

Selected Readings (Papers):