virenVirendra Singh, Ph.D(NAIST, Japan)

 

 

 

Contact Information:

 

E-mail: viren@serc.iisc.ernet.in, virendra@computer.org

 

Tel: +91-80- 2293 3421 (Direct), 2360 0654 (Extn - 212)

 

Fax: +91-80- 2360 2648

 

Postal Address:

Room No. - 212

Supercomputer Education and Research Centre (SERC)

Indian Institute of Science (IISc)

Bangalore - 560 012, India

 

My Calendar

 

 

Moving to IIT Bombay on 15 December 2011

New Address:

Virendra Singh

Associate Professor

Department of Electrical Engineering

Indian Institute of Technology Bombay, Mumbai - 400 076, India

Tel: +91-85535-22109

E-mail: viren@ee.iitb.ac.in, virendra@computer.org

 

New:

Requirement: Post Doctoral Fellows/ Research Associates

 

Funding: DST-JST funding, DST-RFBR

 

Papers: ATS papers, ICCD paper, VLSI-SOC paper, SOCC tutorial

 

Conferences: DRV`11, IWPVTD`11, WRTLT`11, ATS`11, RASDAT`12, Workshop in honour of Prof. Fujiwara

 

Courses: SE-286, E0-285

 

 

Publications Teaching Funding Professional Activities Students Visitors RASDAT IWPVTD

 

 

 

 

Associated Lab.: Computer Design and Test Lab. (CDTL)

 

 

Research Interest:

 

  • VLSI Testing and Verification
  • Processor architecture & micro-architecture
  • Fault-tolerant computing
  • Robust design and architectures
  • Self-healing system design
  • SoC/NoC design and test
  • Post Silicon Debug
  • High level synthesis
  • Formal verification
  • Trusted computing
  • FPGA based acceleration
  • Trusted hardware design

 

 

Education:

 

  • Ph.D (Computer Science) - (2002-2005)

Nara Institute of Science and Technology (NAIST)

Kansai Science City, Nara, Japan

Advisor: Prof. Hideo Fujiwara

Co-Advisors: Prof. Kewal K. Saluja (Univ. of Wisconsin-Madison, USA)

and Prof. Michiko Inoue (NAIST)

Thesis: Instruction-Based Self-Testing of Performance Oriented Faults in Modern Processors

  • M.E (Electronics & Communication) - (1994-1996)

Malaviya National Institute of Technology (MNIT)

Jaipur (Rajasthan) India

Advisor: Prof. MS Gaur

  • B.E (Hons) in Electronics & Communication - (1990-1994)

Malaviya National Institute of Technology (MNIT)

Jaipur (Rajasthan)

 

 

Professional Experience:

 

 

 

Publications: List of my publications

 

Recent Publications:

 

In 2011

 

  • Pramod Subramanyan, Virendra Singh, Kewal Saluja, and Erik Larsson, `Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors`, 29th IEEE International Conference on Computer Design (ICCD) 2011, Amherst, MA, USA, October 2011
  • Mohammed Abdul Razzaq, Virendra Singh, and Adit Singh, `SSTKR: Secure and testable scan design through test key randomization`, 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov. 2011
  • Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Test and diagnosis of analog circuits using moment generating functions`, 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov. 2011
  • Manas Puthal, Virendra Singh, MS Gaur and Vijay Laxmi, `C-Routing: An adaptive hierarchical NoC routing methodology`, 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2011, Hongkong, China, October 2011
  • Anzhela Matrosova, Virendra Singh, Alexey Melnikov, and Ruslan Mukhamedov, `Selection of state variables for partially enhanced scan`, 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011.
  • Mohammad Abdul Razzaq, Alok Baluni, Ram Rakesh Jangir, Virendra Singh, and Masahiro Fujita, `On synthesis of degradation aware circuits at higher level of abstraction`, 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011.
  • Pawan Kumar and Virendra Singh, Efficient regular expression pattern matching using cascaded automata architecture for network intrusion detection system`, 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011.
  • V. Prasanth, Virendra Singh, and Rubin Parekhji, `Reduced overhead soft error mitigation methodology using error control coding technique`, 17th IEEE International On-Line Test Symposium (IOLTS) 2011, Athens, Greece, July 2011.
  • Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Level of confidence evaluation and its usage for roll-back recovery and checkpoint optimization`, Workshop on Dependable and Secure Nanocomputing (WDSN) 2011, Hongkong, China, May 2011
  • Vinutha Konandur, Virendra Singh, MS Gaur, and Anzhela Matrosova, `Fault Grading at Higher Level of Abstraction`, IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May 2011
  • A. Matrosova, S. Ostanin, A. Milnikov, and Virendra Singh, `Using AND-OR tree for path delay faults`, IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May 2011
  • Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Study on level of confidence for rollback recovery with check-pointing`, Workshop on Dependability Issues in Deep-submicron Technologies (DDT) 2011, Trondheim, Norway, May 2011
  • Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Nonlinear analog circuit test and diagnosis under process variation using V-transform coefficients`, 29th IEEE VLSI Test Symposium (VTS), 2011, California, USA, May 2011
  • Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Testing linear and non-linear analog circuits using moment generation functions`, 12th IEEE Latin American Test Workshop (LATW) 2011, Porto de Galinhas, Brazil, March 2011
  • Chao Han, Adit Singh, and Virendra Singh, `Efficient partially enhanced scan for high coverage delay testing`, 2011 Joint IEEE International Conference on Industrial Technology and 43rd Southeastern Symposium on System Theory (ICIT-SSST) 2011, Auburn, USA, March 2011
  • Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Distinguishing process variation induced faults from manufacturing defects in analog circuits using V-transform coefficients`, 2011 Joint IEEE International Conference on Industrial Technology and 43rd Southeastern Symposium on System Theory (ICIT-SSST) 2011, Auburn, USA, March 2011
  • Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, `SEU tolerant SRAM cell`, International Symposium on Quality Electronic Design (ISQED) 2011, Santa Clara, CA, USA, March 2011
  • Naveen Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `Traffic aware topology generation methodology for application specific NoC`, IEEE International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan 2011
  • Navaneeth Rameshan, Mark Zwolinski, Vijay Laxmi, M.S. Gaur, Virendra Singh, and Lalith P., `Acceleration of functional validation using GPGPU`, IEEE International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan 2011

Selected Publications (Before 2011):

 

  • [Book Chapter] Dimitar Nikolov, Mikael Vayrynen, Urban Ingelson, Virendra Singh, and Erik Larsson, `Optimizing Fault Tolerance for Multi-Processor System-on-Chip`, Design and Test Technology for Dependable Systems-on-Chip, Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, 2010, Hardcover, ISBN:978-1-6096-0212-3.

 

  • Prasanth V., Virendra Singh, and Rubin Parekhji, `Robust detection of soft errors using delayed capture methodology`, IEEE International Online Testing Symposium (IOLTS) 2010, Corfu, Greece, July 2010

 

  • Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Energy efficient fault tolerance in chip multiprocessors using critical value forwarding`, 40th IEEE International Conference on Dependable Systems and Networks (DSN), Chicago, IL, USA, June 2010.

 

  • Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Genetic algorithm based topology generation for application specific network-on-chip`, IEEE International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France, May 2010.

 

  • Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, and Adit Singh, `Modified T-FF bases scan cell for RAS`, 15th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May 2010.

 

  • Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach`, 15th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May 2010.

 

  • Pramod Subramanyam, Virendra Singh, Kewal Saluja, and Erik Larsson, `A low cost redundant execution architectures for Chip multiprocessors`, Design Automation and Test in Europe (DATE) 2010, Dresden, Germany, March 2010.

 

  • Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Estimating error probability and its application for optimizing roll-back recovery with checkpointing`, IEEE Symposium on Electronic Design, Test & Applications (DELTA) 2010, Ho Chi Minh , Vietnam, Jan 2010

 

  • Suraj Sindia, Virendra Singh, and Vishwani D. Agrawal, `Parametric Fault Diagnosis of Nonlinear Analog Circuits using Polynomial Coefficients`, 23rd International Conference on VLSI Design (ICVD) 2010, Bangalore, Jan 2010.

 

  • Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Designing Application Specific Irregular Topology for Network-on-Chip`, 17th International Conference on Advanced Computing and Communications (ADCOM) 2009, Bangalore, Dec 2009.

 

  • Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `Multi-tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients`, IEEE Asian Test Symposium (ATS) 2009, Taichung, Taiwan, Nov 2009.

 

  • Deepak K.G., Robinson Reyna, Virendra Singh, and Adit Singh, `Leveraging Partial Enhanced Scan for Improved Observabilty in Delay Fault Testing`, IEEE Asian Test Symposium (ATS) 2009, Taichung, Taiwan, Nov 2009.

 

  • Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Vishwani D. Agrawal, `On Minimization of Peak Power during SoC Test`, IEEE European Test Symposium (ETS) 2009, Seville, Spain, May 2009.

 

  • Reshma Jumani, Niraj Jain, Virendra Singh, and Kewal K. Saluja, `DX-Compactor: Distributed X-Compaction for SoC Test`, ACM Annual Great Lake Symposium on VLSI (GLSVLSI) 2009, Boston, USA, May 2009.

 

 

  • Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `Coefficient-Based Parametric Testing of Non-Linear Analog Circuits`, ACM Annual Great Lake Symposium on VLSI (GLSVLSI) 2009, Boston, USA, May 2009.

 

  • Mikael Vayrynen, Virendra Singh, and Erik Larsson, `Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on-Chips`, Intl. Conference on Design Automation and Test in Europe (DATE) 2009, Nice, France, Apr 2009.

 

  • Virendra Singh and Erik Larsson, `On Reduction of Capture Power for Modular System-on-Chip Test`, 9th IEEE WRTLT 2008, pp. 35-40, Sapporo, Japan, Nov 2008.

 

  • Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Instruction-Based Self-Testing of Delay Faults in Pipelined Processors`, IEEE Trans. on VLSI Systems, Vol. 14, No. 11, Nov. 2006, pp. 1203-1215.

 

  • Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Program-Based Testing of Superscalar Microprocessor`, Proceedings of the IEEE 14th North Atlantic Test Workshop, May 2005, pp. 79-86, Berlington, VT, USA, May 2005.

 

  • Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Delay Fault Testing of Processor Cores in Functional Mode`, IEICE Trans. on Information & Systems, Vol. E-88D, No. 3, March 2005, pp. 610-618.

 

 

Funding:

 

Project: Design of Self-healing System Chips

Funding: INR 72 Lakhs

 

  • UK India Education and Research Initiative (UKIERI) grant, with Prof. MS Gaur, MNIT, Jaipur and Prof. Mark Zwolinski, Southampton University, UK - (2009 to 2011)

Project: Multi-Processor Electronic Design Automation

Funding: INR 22 Lakhs

 

  • LSI Technology Research Grant (2009 to 2013)

Project: Techniques to Speedup Loading of Scan Pattern

Funding: INR 40 Lakhs (INR 10 Lakhs per year)

 

        Research grant under strategic Japanese-Indian cooperative program (DST-JST) with Prof. Masahiro Fujita, Tokyo University, Tokyo, Japan (2010 - 2013)

Project: Computer aided design of hardware accelerated Tsunami prediction system

Funding: INR 1.6 Crores

  • Indo Russian (DST-RFBR) joint research grant with Prof. Anzhela Matrosova, Tomsk State University (2011 - 2013)

Project: Synthesis of high quality testable circuits and diagnosis of performance oriented faults

Funding: INR 20 Lakhs

 

  • Indo Russian (DST-RFBR)) joint research grant with Lyudmila Babenko, Taganrog Institute of Rechnology, and Prof. M.S. Gaur, MNIT, Jaipur (2011 - 2013)

Project: Development of techniques for metamorphic malware detection and analysis

 

Teaching:

 

Current Semester (Aug - Dec 2011)

 

 

 

 

Recent Past

 

 

 

 

 

  • MEL-G626: VLSI Testing and Testability (at BITS, Pilani, Aug-Dec 2006)

(VLSI Testing and Formal Verification)

 

 

Other Activities/ Courses:

 

 

  • Co-coordinator, IEP on VLSI Testing & Verification at IISc. (Mar 10-19, 2008)

 

Professional Activities

 

Convener, Computer Design and Test Lab., SERC, IISc

Member, Departmental Curriculum Committee (DCC), SERC, IISc

 

Steering Committee member

  • IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT)
  • IEEE Asian Test Symposium (ATS)
  • IEEE Workshop on RTL and High Level Testing (WRTLT)

 

General Co-Chair - RASDAT (2010, 2011, 2012)

Program Co-Chair - WRTLT 2011

Finance Chair - ATS 2011

Program Co-Chair - DRV 2011

General Co-Chair - IWPVTD 2011

 

Technical Program Committee Member

  • IEEE International Conference on Computer Design (ICCD) - 2011 (Processor architecture track)
  • IEEE Asia Pacific Design Automation
  • IEEE International Symposium on VLSI (ISVLSI) - 2011 (Chennai)
  • IEEE/IFIP International Symposium on Very Large Scale Integration (VLSI-SoC) - 2011 (Hong Kong)
  • Design Automation and Test in Europe (DATE) - 2009 (Nice), 2010 (Dresden)
  • Intl. Conference on VLSI Design - 2010 (Student track chair), 2011 (Test Track Chair), 2012 (TV track chair)
  • VLSI Design and Test Symposium (VDAT) - 2009 (Bangalore), 2010 (Chandigarh)
  • IEEE Workshop on RTL and High Level Testing (WRTLT) - 2009 (Hong Kong), 2010 (Shanghai)
  • Intl. Conference on Risk and Security of Internet and Systems (CRiSIS) - 2009 (Toulouse)
  • Intl. Conf. on Advanced Computing and Communication (ADCOM) - 2009 (track chair)
  • Intl. Workshop on Network on Chip Architectures (NoCArc) - 2009 (New York)
  • Intl. Conf. on Emerging Trends in Engineering and Technology (ICETET) - 2009
  • IEEE Workshop on Design Reliability and Variability (DRV) - 2009 (Austin, USA)
  • IEEE North Atlantic Test Workshop (NATW) - 2010 (New York)

 

 

Current Students:

 

 

Collaborators

 

Visitors

 

Photos