No Title

No.67, 4th Main
AGO's Layout, RMV 2nd Stage
Bangalore 560 054 (India)

tel (work): +91-80-360 0811
tel (home): +91-80-334 5912
e-mail: nandy@serc.iisc.ernet.in

Soumitra Kumar Nandy

Education	Ph. D. (September 1989) Computer Science and Engineering Indian Institute of Science, Bangalore, India M.Sc.(Engg.) (June 1987) Computer Science and Engineering Indian Institute of Science, Bangalore, India B. E.(Hons.) (May 1980) Electronics and Communication Indian Institute of Science, Bangalore, India B.Sc.(Hons.) (May 1977) Physics Indian Institute of Technology, Kharagpur, India

Professional Experience (with last position held)	Jun 97- (to date) Associate Professor Supercomputer Education and Research Center, Indian Institute of Science, Bangalore. Jun 91- May 97 Assistant Professor Supercomputer Education and Research Center, Indian Institute of Science, Bangalore. Mar 90-Jun 91 Senior Scientific Officer (Selection Grade) Supercomputer Education and Research Center, Indian Institute of Science, Bangalore. Sept 87-Mar 90 Senior Scientific Officer Supercomputer Education and Research Center, Indian Institute of Science, Bangalore. Oct 82-Aug 87 Scientific Officer Supercomputer Education and Research Center, Indian Institute of Science, Bangalore. May 80-Oct 82 Computer Engineer, M/S. ORG Systems, Bangalore

Publications	Over sixty publications in international journals and conference proceedings spanning areas of high performance computing, mobile multimedia computing, reconfigurable domain specific architectures and VLSI design automation.

Other Professional Recognitions	Recent Technical Programme Committee Memberships: 1. International Conference on High Performance Computing 2. International Conference on VLSI Design

Visiting Assignments

Sept 99-Oct 99 Visiting Professor Network Theory Section, Delft University of Technology, Delft, The Netherlands. Project: Quality of Service in Mobile Multimedia Computing

Mar 97-Apr 97 Visiting Professor Network Theory Section, Delft University of Technology, Delft, The Netherlands. Project: Performance Modeling of Multi-threaded Architectures in PAMELA

Sep 96-Dec 96 Visiting Scientist Network Theory Section, Delft University of Technology, Delft, The Netherlands. Project: Multi-threaded DSP Processor Architecture

Oct 93-Sept 94 Visiting Scientist, MIT, Cambridge, MA Member MIT-Motorola *T-NG Design team Project: Architecture of Shared Memory Cache Coherence Module

May 93-Jun 93 Visiting Scientist Network Theory Section, Delft University of Technology, Delft, The Netherlands. Project: Architectural Synthesis of VLSI systems for Fast Interaction Time Rendering of Artificial Photo Realistic Scenes

Jul 91-Aug 91 Visiting Scientist Network Theory Section, Delft University of Technology, Delft, The Netherlands. Project: Workshop on Parallel Algorithms and Architectures

Aug 90-Oct 90 Visiting Scientist Network Theory Section, Delft University of Technology, Delft, The Netherlands. Project: Architectural Synthesis of VLSI systems

Aug 85-Feb 86 Visiting Scientist Department of Computer Science, State University of New York at Stony Brook, New York Project: Development of VLSI CAD Tools

Research Supervision

Ph.D. Theses supervised : 5, MSc.(Engg.) theses supervised: 9, and Undergraduate projects supervised : 50.

Industry Projects

Principal investigator for the research projects:

1.: Hardware-Software Co-Design of High Performance VLSI Systems with Philips Research Laboratories, Eindhoven, The Netherlands.
2.: Design of High Performance VLSI Subsystems for DSP applications with ST Microelectronics.
3.: Power Estimation and Modeling at Behavioral level, and issues in Power Management for Digital Signal Processors with ST Microelectroonics Pvt. Ltd.

Important Publications

High Performance Computing

1.: S. Balakrishnan and S. K. Nandy, ``Performance Evaluation of Multithreaded Architectures for Media Processing Applications'', proceedings of the IEEE International Symposium on Circuits and Systems May 28 - May 31, 2000, Geneva Switzerland (to appear).
2.: M. Srikanth Rao and S. K. Nandy, ``Power Minimization using Control Generated Clocks'', proceedings of the 37th ACM/IEEE Design Automation Conference, June 5 - 9, 2000, Los Angeles USA (to appear)
3.: M. Srikanth Rao and S. K. Nandy,``Controller Redesign based Clock and Register Power Minimization'', proceedings of the IEEE International Symposium on Circuits and Systems May 28 - May 31, 2000, Geneva Switzerland (to appear).
4.: S. Balakrishnan and S. K. Nandy, ``Multithreaded Architectures for Media Processing'', proceedings of the 1st Workshop on Media Processors and DSPs (MP-DSP) Haifa, Israel, November 15, 1999, held in Conjunction with the 32nd Annual International Symposium on Microarchitecture, November 16-18, 1999.
5.: S. K. Nandy, S. Balakrishnan and Ed Deprettere, ``SYMPHONY : A Scalable High Performance Architecture Framework for Media Applications'', Proceedings of the 5th International Conference on Advanced Computing, December 15-17, Chennai, 1997.
6.: S. Balakrishnan, S. K. Nandy, and Arjan van Gemund, ``Modeling Multi-threaded Architectures in PAMELA for Real-time High Performance Applications'', Proceedings of the 4th International Conference on High Performance Computing, Bangalore, India, December 18-21, 1997.
7.: S. Balakrishnan and S. K. Nandy, ``Arbitrary Precision Arithmetic-SIMD Style'', proceedings of the 11th International Conference on VLSI Design, Chennai, India, January 4-7, 1998.
8.: H. Saroja Devi and S. K. Nandy, ``Obviating the need for Directory in Auto-invalidating Caches, Proceedings of the 6th International Conference on Advanced Computing, December 14-16, Pune, 1998.
9.: S. K. Nandy, S. Balakrishnan, and Ranjani Narayan, ``Concerting Processors for Domain Specific High Performance Architectures'', Proceedings of the 2nd International Conference on High Performance Computing, New Delhi, India, Dec 27 - Dec 30, 1995.
10.: S. K. Nandy and Ranjani Narayan, ``An Incessantly Coherent Cache Scheme for Shared Memory Multi-threaded Systems'', Proceedings of the First International Workshop on Parallel Processing, Bangalore, India, December 26-31, 1994, pp. 240-245.
Mobile Multimedia Computing
1.: Abhijit Lele, S. K. Nandy and D.H.J. Epema, ``Design Space Exploration for Providing QoS within the Harmony Framework'', Proceedings of the International Conference on Multimedia and Expo 2000, July 31 - August 2, 2000, New York (to appear).
2.: Abhijit Lele and S. K. Nandy, ``HARMONY - A Framework for providing Quality of Service in Wireless Mobile Computing Environment'', Proceedings of the 6th International Conference on High Performance Computing, December 17-20, 1999, Calcutta, India
3.: Abhijit Lele and S. K. Nandy, ``Can QoS Guarantees be supported for live Video over ATM Networks?'', Proceedings of GLOBECOM '98, Sydney, Australia, November 1998.
Reconfigurable Domain Specific Architecture
1.: S. Ramanathan, S. K. Nandy and V. Visvanathan, ``Reconfigurable Filter Coprocessor Architecture for DSP Applications'', The Journal of VLSI Signal Processing, Kluwer Academic Publishers (to appear).
2.: S. Ramanathan, V. Visvanathan and S. K. Nandy, ``A Computational Engine for Multirate FIR Digital Filtering, Signal Processing, Vol. 79, No. 2, December 1999, Elsevier Science.
3.: S. Ramanathan, V. Visvanathan and S. K. Nandy, ``Synthesis of ASIPs for DSP Algorithms,'' INTEGRATION, the VLSI Journal, Vol. 28, No. 1, pp. 13-32, September 1999, Elesevier Science.
4.: S. Ramanathan, V. Visvanathan and S. K. Nandy, ``Architectural Synthesis of Computational Engines for Subband Adaptive Filtering,'' The Journal of VLSI Signal Processing - Systems for Signal, Image and Video Technology, Vol. 22, No. 3, pp. 173-195, September 1999, Kluwer Academic Publishers.
5.: S. Ramanathan, V. Visvanathan and S.K. Nandy, ``Synthesis of Configurable Architectures for DSP Algorithms,'' In the proceedings of the 12th International Conference on VLSI Design, Jan 7-10, 1999, Goa, India.
Other Publications
1.: Avinash Gautam, V. Visvanathan and S. K. Nandy, ``Automatic Generation of Tree Multipliers using Placement-Driven Netlists'', Proceedings of the International Conference on Computer Design (ICCD '99), October 10 - 13, 1999 (to appear).
2.: S. Ramanathan, V. Visvanathan and S.K. Nandy, ``Architectural Synthesis of Low-Power Computational Engines for LMS Adaptive Filtering,'' Proceedings of the International Conference on Signal Processing Applications and Technology, Toronto, Canada, September 1998.
3.: M. R. Karthikeyan and S. K. Nandy, ``An Asynchronous Architecture for Digital Signal Processors'', Proceedings of the European Design and Test Conference and Exhibition, Paris, March 17-20, 1997.
4.: Vinod Menezes, S. K. Nandy, Biswadip Mitra, ``Signal Compression through Spatial Frequency based Motion Estimation'', Integration the VLSI journal, No. 22, 1997, Elsevier Science Publishers, pp. 115-135.
5.: Debabrata Ghosh and S. K. Nandy, ``Design and Realization of High Performance Wave-Pipelined 8 x 8-bit Multiplier in CMOS Technology'', IEEE transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 1, March 1995, pp. 36-48.