SOUMITRA K. NANDY

Supercomputer Education & Research Center
Indian Institute of Science
Bangalore 560 012, INDIA
e-mail: nandy@serc.iisc.ernet.in
tel(work): 91-80-3341811; 91-80-3092736
tel(home): 91-80-3345912

EXPERTISE AND INTERESTS

• Application Specific Instruction Set Processor (ASIP) Architecture: Design, analysis and development of computational structures targetted for embedded systems on silicon.

• Reconfigurable High Performance Processor Architectures: Design, evaluation and synthesis of processor architectures from parameterized computational structures to meet performance requirements of current day applications on portable and hand held systems.

• Systems on Silicon: Application of hardware-software co-design techniques to explore architecture-algorithm design space, and realization of various architectures from within a single framework.

• Compiling Techniques for Low Power: Compiler optimizations and retargettable code generators for low power.

• Architectural Synthesis of High Performance VLSI Systems: Design and development of an architecture evaluator. Issues involve study and analysis of various mapping and scheduling schemes.

• High Speed Communication Networks and Ubiquitous Computing: Call admission control in ATM networks, QoS guarantees in ATM networks, Network traffic modeling and network topology aggregation for call routing.

• Parallel/Pipelined low latency, high throughput arithmetic unit architectures: Performance-driven multiplier architectures and multiplication algorithms.
• Multi-threaded Architecture: Design and development of a multi-threaded architecture for media applications.

• Global Shared Memory Cache Coherence Protocols: Compiler assisted directory-less shared memory cache coherence protocol for distributed shared memory systems.

EMPLOYMENT HISTORY

Jun 97- (to date)	Associate Professor
	Supercomputer Education and Research Center,
	Indian Institute of Science, Bangalore
Jun 91- May 97	Assistant Professor
	Supercomputer Education and Research Center,
	Indian Institute of Science, Bangalore

Mar 90-Jun 91	Senior Scientific Officer (Selection Grade)
	Supercomputer Education and Research Center,
	Indian Institute of Science, Bangalore
Sept 87-Mar 90	Senior Scientific Officer
	Supercomputer Education and Research Center,
	Indian Institute of Science, Bangalore
Oct 82-Aug 87	Scientific Officer
	Supercomputer Education and Research Center,
	Indian Institute of Science, Bangalore
May 80-Oct 82	Computer Engineer, M/S. ORG Systems, Bangalore

ON-SITE ASSIGNMENTS

Mar 97-Apr 97	Visiting Scientist Network Theory Section,
	Delft University of Technology, Delft, The Netherlands
	Project: Performance Modeling of Multi-threaded Architectures in PAMELA
Sep 96-Dec 96	Visiting Scientist Network Theory Section,
	Delft University of Technology, Delft, The Netherlands
	Project: Multi-threaded DSP Processor Architecture
Oct 93-Sept 94	Visiting Scientist, MIT, Cambridge, MA
	Member MIT-Motorola *T-NG Design team
	Project: Architecture of Shared Memory Cache Coherence Module
May 93-Jun 93	Visiting Scientist Network Theory Section,
	Delft University of Technology, Delft, The Netherlands
	Project: Architectural Synthesis of VLSI systems for
	Fast Interaction Time Rendering of Artificial Photo Realistic Scenes
Jul 91-Aug 91	Visiting Scientist Network Theory Section,
	Delft University of Technology, Delft, The Netherlands
	Project: Workshop on Parallel Algorithms and Architectures
Aug 90-Oct 90	Visiting Scientist Network Theory Section,
	Delft University of Technology, Delft, The Netherlands
	Project: Architectural Synthesis of VLSI systems
Aug 85-Feb 86	Visiting Scientist Department of Computer Science,
	State University of New York at Stony Brook, New York
	Project: Development of VLSI CAD Tools

EDUCATION

Ph. D. (September 1989)	Indian Institute of Science, Bangalore, India
	Computer Science and Engineering
M.Sc.(Engg.) (June 1987)	Indian Institute of Science, Bangalore, India
	Computer Science and Engineering
B. E.(Hons.) (May 1980)	Indian Institute of Science, Bangalore, India
	Electronics and Communication
B.Sc.(Hons.) (May 1977)	Indian Institute of Technology, Kharagpur, India
	Physics

RESEARCH ACTIVITIES / FACILITATION

• Supervisor for 10 Bachelors degree dissertations, 30 Masters degree dissertation, 4 Doctoral and 5 M.Sc.(Engg.) (4 awarded degrees) spanning topics in processor architectures for media applications, architecture synthesis of high performance applications, hardware-software co-design, parallel algorithms and architectures, algorithms for VLSI CAD tools and design of arbitrary precision arithmetic and logic units, and applications of MPEG.

• Set up a laboratory for Computer Aided VLSI Design at the Indian Institute of Science, India. This involved infrastructure setup with state-of-the-art computing facilities with VLSI CAD tools from Technical University, Delft, The Netherlands to carry out full custom and semi-custom VLSI and ASIC design.

• Co-investigator for the following research / consultancy projects:

  1.

  Design Automation of VLSI Systems for Signal Processing. (on-going)

  This project is in collaboration with M/S. NCORE Pvt. Ltd. Bangalore (a leading Information Technology Industry) for development of CAD tools for Architectural Synthesis of Domain Specific Processor Architectures.

  The project is funded by National Micro-electronic Council, Department of Electronics, (Government of India).

  2.

  LSI/VLSI Design Center (funded by National Micro-electronic Council, Department of Electronics, Government of India) for development of Application Specific Integrated Circuits. (Completed)

  3.

  Joint research project ``VLSI Collaboration TUD - IISc.'' between Technical University Delft, The Netherlands and IISc. for design of advanced VLSI CAD tools for architecture synthesis of high performance VLSI systems. (on-going)

  4.

  M/S Hindustan Computers Pvt. Ltd. consultancy project for development of parallel CAD tools for PCB design. (Completed)

TEACHING

• Computer Aided VLSI Design
• Computers and Computing
• Algorithms for VLSI CAD tools
• Computer Graphics

EXTERNAL LECTURES

• Co-Instructor for the one-day tutorial, "Performance Modeling of High Performance Systems", 4th International Conference on High Performance Computing, Bangalore, India, December 18-21, 1997.

AWARDS and RECOGNITIONS

• Member, Technical Programme Committee, VLSI '99 International Conference on VLSI Design to be held in Goa, India during January 7-10, 1999, Goa, India.

• Member, Technical Programme Committee, TENCON '98, IEEE Region 10 Conference, to be held in New Delhi, India during December 17-19, 1998.

• Exhibits Chair, 5th International Conference on High Performance Computing, to be held in Chennai (Madras), India during December 17-20, 1998.

• Exhibits Chair, 4th International Conference on High Performance Computing, held in Bangalore, India during December 18-21, 1997.

• Exhibits Co-Chair, 3rd International Conference on High Performance Computing, held in Trivandrum, India, during December 19-22, 1996.

• Member of the Editorial Board for the international journal ``Integration the VLSI Journal'', Elsevier Science Publishers.

• Elected Divisional Representative of the Computer Society of India (Bangalore Chapter) 1989 - 1990.

• Awarded the National Merit Scholarship to pursue graduate studies for having secured 2nd rank in B.Sc. (Hons.) Physics 1977.

• Awarded the Jagadis Bose National Science Talent Scholarship in India, 1975.

• Awarded the National Science Talent Scholarship, India, 1974.

JOURNAL PUBLICATIONS

1.

Vinod Menezes, S. K. Nandy, Biswadip Mitra, "Signal Compression through Spatial Frequency based Motion Estimation", Integration the VLSI journal, No. 22, 1997, Elsevier Science Publishers, pp. 115-135.

2.

Debabrata Ghosh and S. K. Nandy, ``Design and Realization of High Performance Wave-Pipelined $8 \times 8$-bit Multiplier in CMOS Technology'', IEEE transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 1, March 1995, pp. 36-48.

3.

S. K. Nandy, ``Geometrical Design Rule Check of VLSI layouts in Distributed Computing Environment'', International Journal of Computer Aided VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Vol. 1, No. 2, 1994, Gordon and Breach Science Publishers pp. 127-154.

4.

S. K. Nandy and R. B. Panwar, ``Geometric Design Rule Check of VLSI layouts in Mesh Connected Processors'', International Journal of Computer Aided VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Vol. 1, No. 2, 1994, Gordon and Breach Science Publishers, pp. 135-167.

5.

Debabrata Ghosh and S. K. Nandy, ``A 600-MHz Halfbit Level Pipelined Accumulator-Interleaved Multiplier Accumulator Core'', VLSI SIGNAL PROCESSING VI, IEEE Signal Processing Society, pp. 498-506, 1993.

6.

S. Balakrishnan and S. K. Nandy, ``Quasi Dynamic Approach to Layout Compaction'', Microprocessing and Microprogramming, Vol. 30, 1990, pp. 231-236 (North Holland Publications).

7.

C. E. Prakash and S. K. Nandy, ``VOXEL based Modeling and Rendering Irregular Solids'', Microprocessing and Microprogramming, Vol. 30, 1990, pp. 341-346 (North Holland Publications).

8.

S. K. Nandy, C. Sudha Madhuri, Anuradha. D, and Rajat Moon a, ``K-d tree based Gridless Maze Routing on Message Passing Multiprocessor System'', Journal of the IETE (special issue on microelectronics), Vol. 36, Nos. 3 & 4, 1990.

9.

G. Vidyamurthy and S. K. Nandy, ``On the Reconfigurability of Hardware Accelerators for VLSI CAD tools'', Journal of the IETE (special issue on microelectronics), Vol. 36, Nos. 3 & 4, 1990.

10.

S. K. Nandy and L. M. Patnaik, "Algorithms for Incremental Compaction of Geometrical Layouts", Computer-Aided Design, Butterworth and Co. (Publishers) Ltd., Vol. 19, No.5, June 1987, pp. 257-265.

11.

S. K. Nandy and L. M. Patnaik, "Linear Time Geometrical Design Rule Checker based on Quadtree representation of VLSI Mask Layouts", Computer-Aided Design, Butterworth & Co. (Publishers) Ltd., Vol. 18, No. 7, September 1986, pp. 380-388.

12.

S. K. Nandy and L. M. Patnaik, "A Study of Placement Algorithms through Trial Interchange of Logic Modules", Computers-Aided Design, Butterworth & Co. (Publishers) Ltd., Vol. 17, No. 5, June 1985, pp 211-214.

PUBLICATIONS IN RIGOROUSLY REFEREED CONFERENCES (deemed at par with journal publications)

1.

S. Ramanathan, V. Visvanathan and S.K. Nandy, "Synthesis of Configurable Architectures for DSP Algorithms," 1999 Intl. Conf. on VLSI Design (to appear).

2.

H. Saroja Devi and S. K. Nandy, "Obviating the need for Directory in Auto-invalidating Caches, Proceedings of the 6th International Conference on Advanced Computing, December 14-16, Pune, 1998 (to appear).

3.

Abhijit Lele and S. K. Nandy, "Can QoS Guarantees be supported for oive Video over ATM Networks?", Proceedings of GLOBECOM '98, Sydney, Australia, November 1998 (to appear).

4.

S. Ramanathan, V. Visvanathan and S.K. Nandy, "Architectural Synthesis of Low-Power Computational Engines for LMS Adaptive Filtering," Proceedings of the International Conference on Signal Processing Applications and Technology, Toronto, Canada, September 1998 (to appear).

5.

S. Balakrishnan and S. K. Nandy, ``Arbitrary Precision Arithmetic-SIMD Style'', proceedings of the 11th International Conference on VLSI Design, Chennai, India, January 4-7, 1998.

6.

S. K. Nandy, S. Balakrishnan and Ed Deprettere, ``SYMPHONY : A Scalable High Performance Architecture Framework for Media Applications'', Proceedings of the 5th International Conference on Advanced Computing, December 15-17, Chennai, 1997.

7.

S. Balakrishnan, S. K. Nandy, and Arjan van Gemund, ``Modeling Multi-theraded Architectures in PAMELA for Real-time High Performance Applications'', Proceedings of the 4th International Conference on High Performance Computing, Bangalore, India, December 18-21, 1997.

8.

M. R. Karthikeyan and S. K. Nandy, ``An Asynchronous Architecture for Digital Signal Processors'', Proceedings of the European Design and Test Conference and Exhibition, Paris, March 17-20, 1997.

9.

Vinod Menezes, S. K. Nandy, Biswadip Mitra, "Spatial Frequency based Motion Estimation for Image Sequence Compression", Proceedings of the 3rd International Conference on High Performance Computing, Trivandrum, India, December 19-22, 1996.

10.

S. K. Nandy, S. Balakrishnan, and Ranjani Narayan, ``Concerting Processors for Domain Specific High Performance Architectures'', Proceedings of the 2nd International Conference on High Performance Computing, New Delhi, India, Dec 27 - Dec 30, 1995.

11.

S. K. Nandy and Ranjani Narayan, ``An Incessantly Coherent Cache Scheme for Shared Memory Multi-threaded Systems'', Proceedings of the First International Workshop on Parallel Processing, Bangalore, India, December 26-31, 1994, pp. 240-245.

12.

A. Giri, V. Visvanathan, S. K. Nandy, and S. K. Ghoshal, ``High Speed Digital Filtering on SRAM-Based FPGAs'', Proceedings of the seventh international conference on VLSI Design, January 5-8, 1994, Calcutta, India.

13.

G. N. Rathna, S. K. Nandy and K. Parthasarathy, ``A Methodology for Architecture Synthesis of Cascaded IIR Filters'', Proceedings of the seventh international conference on VLSI Design, January 5-8, 1994, Calcutta, India.

14.

Debabrata Ghosh, S. K. Nandy and K. Parthasarathy, ``TWTXBB: A Low Latency, High Throughput Multiplier Architecture using a New $4 \rightarrow 2$ Compressor'', Proceedings of the seventh international conference on VLSI Design, January 5-8, 1994, Calcutta, India.

15.

Debabrata Ghosh, Shamik Sural and S. K. Nandy, ``A 600MHz Half-Bit Level Pipelined Multiplier Macrocell'', Proceedings of the seventh international conference on VLSI Design, January 5-8, 1994, Calcutta, India.

16.

Debabrata Ghosh and S. K. Nandy, ``A 600-MHz Halfbit Level Pipelined Accumulator-Interleaved Multiplier Accumulator Core'', 1993 IEEE Workshop on VLSI Signal Processing, October 20 - 22, Veldhoven, The Netherlands.

17.

Debabarata Ghosh and S. K. Nandy, ``A 400MHZ Wave-Pipelined $8 \times 8$-bit Multiplier in CMOS Technology'', International Conference on Computer Design (ICCD'93), Cambridge, Massachusetts, USA, October 3-6, 1993.

18.

S.K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, P. Chauhan, ``A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multi-threaded VLSI Processor Array'', Proceedings of the 1993 International Conference on Parallel Processing, Illinois, August 1993.

19.

Debabrata Ghosh, S. K. Nandy, P. Sadayappan and K. Parthasarathy, ``Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving'', proceedings of the 30th ACM/IEEE Design Automation Conference, Dallas, USA.

20.

Debabrata Ghosh, S. K. Nandy, K. Parthasarathy and V. Visvanathan, ``NPCPL : Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs'', Proceedings of the fifth international conference on VLSI Design (VLSI Design '93), Bombay, India.

21.

N. B. Bhat and S. K. Nandy, "Special Purpose Architecture for Accelerating Bitmap DRC", Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vagas, 1989, pp. 674-677.

22.

S. K. Nandy, Rajat Moona and S. Rajagopalan, "Linear Quadtree Algorithms on the Hypercube", Proceedings of the International Conference on Parallel Processing, vol. 3, pp. 227-229, 1988.

23.

S. K. Nandy and I. V. Ramakrishnan, "Dual Quadtree representation for VLSI Designs", Proceedings of the 23rd ACM/IEEE Design Automation Conference, Las Vagas, July 1986, pp. 663-666.

TECHNICAL REPORTS & CONFERENCE PUBLICATIONS

1.

S. K. Nandy and S. Balakrishnan, "Modeling and Design of High Performance VLSI Processor Arrays", Conference on Emerging Microelectronics and Interconnection Technologies, EMIT '96, February 12 - 16, 1996, Bangalore, India (Invited Paper).

2.

John Morris, et al, ``Hermes: Communicating *T-NGs'', LCS, CSG-Memo 358, Technical Report, Massachussetts Institute of Technology, June 1994, "LIMITED DISTRIBUTION".

3.

B.S. Ang, D. Chiou, J.C. Hoe, X.-W. Shen, J. Morris, S.K. Nandy and M.J. Beckerle, ``ACD Requirements'', LCS, CSG-Memo 357, June 1994, "LIMITED DISTRIBUTION".

4.

S. K. Nandy and Ranjani Narayan, ``An Incessantly Coherent Cache Scheme for Shared Memory Multi-threaded Systems'', LCS, CSG-Memo 356, Technical Report, Massachussetts Institute of Technology, September 15, 1994.

5.

Ranjani Narayan, S.K. Nandy, V. Rajaraman, P.K. Fangaria, ``A Space and Time Efficient Global Memory Support on Multicomputer Systems'', Proceedings of the IASTED International Conference on Modelling and Simulation, Pittsburgh during May 1993.

6.

G. N. Ratna, M. K. Sridhar, K. Parthasarthy and S. K. Nandy, ``Floating point processor with gate-array technology: A preliminary design'', 3rd International Workshop on VLSI Design, 1990.

7.

S. Balakrishnan and S. K. Nandy, ``Quasi Dynamic Approach to Layout Compaction'', EUROMICRO 90, Sixteenth Symposium on Microprocessing and Microprogramming, pp. 231-236.

8.

C. E. Prakash and S. K. Nandy, ``VOXEL based Modeling and Rendering Irregular Solids'', EUROMICRO 90, Sixteenth Symposium on Microprocessing and Microprogramming, pp. 341-346.

9.

S. K. Nandy, M. S. Kailasnath and Ranjani Narayan, ``Parallel Logic Simulation in a Dataflow Oriented Multiprocessor System'', Proceedings of the PARCOM 90, pp. 341-348.

10.

N. B. Bhat and S. K. Nandy, "New Algorithms for Hardware Acceleration of DRC", Proceedings of the 2nd International Workshop on VLSI Design, Bangalore, India, 1988, pp 382-413.

11.

R. B. Panwar and S. K. Nandy, "Parallel Architecture for Boundary Following of Regions of an Image stored as a Linear Quadtree", Proceedings of the 26th Annual Allerton Conference, on Communication, control and Computing, September 1988, pp. 1025- 1034.

12.

M. K. Srinivas, S. K. Nandy and R. Moona, "Implementation Issues of a Two-Layer Block Router Based on Lee's Algorithm on Personal Computers", TENCON, August 1987, Seoul, Korea, pp. 774-778.

13.

S. K. Nandy and L. M. Patnaik, "Placement through Pairwise Interchange among Connected and Unconnected Logic Modules", Proceedings of the 23rd Annual Allerton Conference on Communications, Control and Computing, October 2-4, 1985, pp. 686- 687.

14.

S. K. Nandy and L. M. Patnaik, "A Hybrid Technique for Placement of Logic Modules", Proceedings of the IEEE International Conference on Computers, Systems and Signal Processing, 1984, pp. 1460-1463.

PAPERS COMMUNICATED

1.

S. Ramanathan, V. Visvanathan and S. K. Nandy, " A Universal Low-Power Computational Engine for Convolution-Type Computations", 36th ACM/IEEE Design Automation Conference, 1999.

2.

Abhijit Lele and S. K. Nandy, "A Scalable Energy Efficient Gigabit ATM Switch", 36th ACM/IEEE Design Automation Conference, 1999.

3.

Avinash Gautam, V. Visvanathan and S.K. Nandy, "Automatic Generation of Tree Multipliers Using Placement-Driven Netlists," IEEE Trans. VLSI Systems.

4.

S. Ramanathan, V. Visvanathan and S. K. Nandy, ``Architectural Synthesis of Low-Power Computational Engines for Subband Adaptive Filtering,'' Journal of VLSI Signal Processing, Kluwer Academic Publishers (submitted June 1998).

5.

S. Ramanathan, V. Visvanathan and S. K. Nandy, ``Architectural Synthesis of Low-Power Computational Engines for Subband Adaptive Filtering,'' Journal of VLSI Signal Processing, Kluwer Academic Publishers (submitted June 1998).

6.

S. Ramanathan, V. Visvanathan and S. K. Nandy, ``Synthesis of ASIPs for DSP Algorithms,'' INTEGRATION, the VLSI Journal, Elesevier Science (submiited July 1998)

7.

S. Ramanathan, V. Visvanathan and S. K. Nandy, ``A Low-Power Computational Engine for Multirate FIR Digital Filtering,'' Signal Processing, Elsevier Science (submitted August 1998)