Domain Specific High Performance Processor Architectures:
Design and evaluation of processor architectures for high throughput
and low latency applications targeted for VLSI realization.
Systems on Silicon: Application of hardware-software
co-design techniques to explore architecture-algorithm design space, and
realization of various architectures from within a single framework.
Architectural Synthesis of High Performance VLSI Systems:
Design and development of an architecture evaluator. Issues involve study and
analysis of various mapping and scheduling schemes.
High Speed Communication Networks and Ubiquitous Computing:
Call admission control in ATM
networks, QoS guarantees in ATM networks, Network traffic modeling for
multi-media applications.
Parallel/Pipelined low latency, high throughput arithmetic unit
architectures: Performance-driven multiplier architectures and multiplication algorithms
Parallel Algorithms Algorithms for VLSI CAD tools and algorithm for
pattern match.
Multi-threaded Architecture: Design and development of a multi-threaded
architecture for fast interaction time rendering of artificial photo realistic
scenes.
Global Shared Memory Cache Coherence Protocols: New directory-less
shared memory cache coherence protocol for MPP systems
ASIPs for embedded systems -- Issues and solutions.
