Soumitra Kumar Nandy Professor   Computer Aided Design Laboratory  Supercomputer Education and Research Centre  Indian Institute of Science  Bangalore 560 012  India.

Research Interests

• Application Specific Instruction Set Processor (ASIP) Architecture: Design, analysis and development of computational structures targetted for embedded systems on silicon.
• Reconfigurable High Performance Processor Architectures: Design, evaluation and synthesis of processor architectures from parameterized computational structures to meet performance requirements of current day applications on portable and hand held systems.
• Systems on Silicon: Application of hardware-software co-design techniques to explore architecture-algorithm design space, and realization of various architectures from within a single framework.
• Compiling Techniques for Low Power: Compiler optimizations and retargettable code generators for low power.
• Architectural Synthesis of High Performance VLSI Systems: Design and development of an architecture evaluator. Issues involve study and analysis of various mapping and scheduling schemes.
• High Speed Communication Networks and Ubiquitous Computing: Call admission control in ATM networks, QoS guarantees in ATM networks, Network traffic modeling and network topology aggregation for call routing.
• Parallel/Pipelined low latency, high throughput arithmetic unit architectures: Performance-driven multiplier architectures and multiplication algorithms.
• Multi-threaded Architecture: Design and development of a multi-threaded architecture for media applications.
• Global Shared Memory Cache Coherence Protocols: Compiler assisted directory-less shared memory cache coherence protocol for distributed shared memory systems.

Students

Former Students

Representative Publications

• Dynamic Traffic Profiling for Efficient Link Bandwidth Utilization in QoS Routing, in the proceedings of the 9th Asia-Pacific Conference on Communications, Penang, Malaysia, September 2003.
• Simultaneous MultiStreaming fo Complexity Effective VLIW Architectures, in the proceedings of the Advances in Computer System Architecture (ACSAC 2003), Japan, September 2003.
• Evaluating Compiler Support for Complexity-Effective Network Procesing, in the proceedings of the workshop on Complexity Effective Design, held in conjuction with 30th International Symposium on Computer Architecture (ISCA), San Diego, California, June 2003.
• On the Benefits of Speculative Trace Scheduling in VLIW Processors, in the Proceedings of Parallel and Distributed Processing Techniques and Applications, PDPTA'02, Las Vegas, USA, June 2002.
• Speculative Trace Scheduling in VLIW Processors, In the Proceedings of International Conference on Computer Design, ICCD'02, Freiburg, Germany, September 2002.
• Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW Processors, In the Proceedings of 15th Symposium on Integrated Circuits and Systems Design, SBCCI'02, Brazil, September 2002.
• Coherence Buffer: An Architectural Support for Imposing Early and Local Cache Coherence in Distributed Shared-Memory Multiprocessors, Technical Report, CAD Lab, May 2002.
• Multithreaded Architectures for Media Processing, In the proceedings of the 1st Workshop on Media Processors and DSPs (MP-DSP), Haifa, Israel, November 15, 1999, in conjunction with the 32nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 32), November 16-18, 1999.
• HARMONY: A Framework for providing Quality of Service in Wireless Mobile Computing Environment, In the proceedings of the Sixth International Conference on High Performance Computing, December 17-20, 1999, Calcutta, India (to appear).
• SYMPHONY: A Scalable High Performance An Architecture Framework for Media Applications, In the proceedings of the Fifth International Conference on Advanced Computing, December 15-17, 1997, Chennai (Madras), India
• Modeling Multithreaded Architectures in PAMELA for Real-time High Performance Applications, In the proceedings of the Fourth International Conference on High Performance Computing, December 18-21, 1997, Bangalore, India.
• Arbitrary Precision Arithmetic -- SIMD Style, In the proceedings of the Eleventh International Conference on VLSI Design, January 4-8, 1998, Chennai (Madras), India.
• Can QoS Guarantees be Supported for Live Video Over ATM Networks, In the proceedings of the IEEE Global Telecommunications Conference, GLOBECOM '98, Nov 8-12, Sydney, Australia.
• Obviating the need for Directory in Auto-invalidating Caches, In the proceedings of the Sixth International Conference on Advanced Computing, December 14-16, 1998, Pune, India.
• Synthesis of Configurable Architectures for DSP Algorithms, In the proceedings of the 12th International Conference on VLSI Design, Jan 7-10, 1999, Goa, India.
• Architectural Synthesis of Low-Power Computational Engines for LMS Adaptive Filtering, In the Proceedings of the International Conference on Signal Processing Applications and Technology, Toronto, Canada, September 1998.
• Architectural Synthesis of Computational Engines for Subband Adaptive Filtering, The Journal of VLSI Signal Processing - Systems for Signal, Image and Video Technology, Vol. 22, No. 3, pp. 173-195, September 1999, Kluwer Academic Publishers.
• A Computational Engine for Multirate FIR Digital Filtering, Signal Processing, Vol. 79, No. 2, December 1999, Elsevier Science.
• Synthesis of ASIPs for DSP Algorithms, Integration, the VLSI Journal, Vol. 28, No. 1, pp. 13-32, September 1999, Elsevier Science.

Events

• Thesis Colloquium (16th June, 2000) -- HARMONY: A QoS Architecture for Mobile Computing

 
• Curriculum Vitae (Last Updated June 9 2000)