E0-243 : Computer Architecture

Course Outline:

  • Processor Architecture: Instruction-Level Parallelism, Superscalar and VLIW architecture; Multi-core processors;
  • Memory Subsystem: Multilevel caches, Caches in multi-core processors, Memory controllers for multi-core systems;
  • Multiple processor systems: taxonomy, distributed and shared memory system, memory consistency models, cache coherence, and Interconnection networks;
  • Advanced topics in architecture

Class Timing :    WF 8.00 - 9.30 a.m.


Text

  • D. A. Patterson and J. L. Hennessy, "Computer Architectures: A Quantitative Approach'', Morgan Kaufmann Publishers, 4th Edition
  • Current Literature.
Reading Materials