E0-243 : Computer Architecture

Course Outline:

• Processor Architecture: Instruction-Level Parallelism, Superscalar and VLIW architecture; Multi-core processors;
• Memory Subsystem: Multilevel caches, Caches in multi-core processors, Memory controllers for multi-core systems;
• Multiple processor systems: taxonomy, distributed and shared memory system, memory consistency models, cache coherence, and Interconnection networks;
• Advanced topics in architecture

• D. A. Patterson and J. L. Hennessy, "Computer Architectures: A Quantitative Approach'', Morgan Kaufmann Publishers, 4th Edition
• Current Literature.

• J.E. Smith and G.S. Sohi. Microarchitecture of Superscalar Processors. Proceedings of the IEEE, 83(12), 1609-1624.
• K.C. Yeager. The MIPS R10000 Superscalar Processor. IEEE MICRO, 28-40, April 1996.
• S. Adve and K. Gharachorloo, Shared Memory Consistency Models: A Tutorial, IEEE Computer, 1995.
• T. Austin, E. Larson, and D. Ernst, SimpleScalar: An Infrastructure for Computer System Modeling , IEEE Computer, Feb. 2002.
• R.E. Wunderlich, T. Wenisch, B. Falsafi and J.C.Hoe, SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling, 30th ISCA 2003.

Evaluation:


• Mid-term :         20 marks (on Sept. 13 and Oct. 27, 2017)
• Term-Project:     30 marks
• Proposal Due by Oct. 1, 2017
• First Review by Oct. 31, 2017
• Report and Demo/Presentation : Nov. 28, 2017
• Final Exam :      50 marks (on Nov. 30, 2017)
  
Lecture Notes:


• L0: Introduction    pps    pdf   
• L1: ILP Processors    pps    pdf   
• L2: Parallel Architecture    pps    pdf   
General Rules: Academic integrity must be maintained in assignments/term projects and exams.